1. Field of the Invention
The invention relates to a method for fabricating connection terminals of a circuit board, and more particularly, to a method for fabricating metal connection materials of different heights and sizes simultaneously on connection pads of the circuit board.
2. Description of the Related Art
In the recent years, electrical products such as notebook (NB) computer, mobile phone, personal digital assistant (PDA), and digital camera are developed in a more and more compact size while their operation speeds are getting faster by demands. These dynamic changes have brought in many challenges for package technology of the semiconductor chip. As the product designs are directed towards achieving minimization, high speed and multi-functions, flip-chip technique has been more widely applied as a standard chip packaging technique. And passive devices, such as resistors, capacitors, and inductors are formed in those electrical devices to improve their electrical quality. These passive devices are typically attached by surface mounting technique (SMT) to the chip carrier of the circuit board. This results both pre-solder bumps and surface mount metal connection elements to be present and to form solder materials of different heights and sizes on the circuit board.
Referring to FIG. 1, a plurality of metal bumps 11 are formed on electrode pads 12 of the chip 13 by flip-chip technique, and a plurality of pre-solder bumps 14 made of soldering material are formed on connection pads 15 of the circuit board 16. The pre-solder bumps 14 are soldered to the corresponding metal bumps 11 at a reflow soldering temperature sufficient to melt the pre-solder bumps 14 for forming solder bonds 17. An underfill material 18 is further adopted to achieve coupling of the chip 13 to the circuit board 16 to ensure integrity and reliability for connection between the chip 13 and circuit board 16.
The pre-solder bumps provide mechanical coupling and electrical connection between the semiconductor chip and the circuit board. The pre-solder bumps may also be connected to different surface-mounted semiconductor devices, such as passive devices so as to provide better electrical quality for the electrical devices. However, it is necessary to electroplate soldering material of different heights and sizes on the connection pads of the circuit board to correspond to different surface-mounted semiconductor devices. As a result, the connection terminals of different heights are formed to connect to different types of the surface-mounted semiconductor devices.
Currently, the common method adopted to form the soldering material on the connection pads of the circuit board involves a template printing technique. As illustrated in FIG. 2, a solder mask layer 21 is formed on a circuit board 20 completed with circuit wiring to expose a plurality of connection pads 22. A mold plate 23 having a plurality of openings 23a is disposed on the solder mask layer 21 of the circuit board 20 so that solder stacks (not shown) are formed through the openings 23a on the connection pads 22.
Furthermore, a plurality of solder balls are implanted on the bottom surface of the circuit board to provide electrical connections with the external electrical devices when the circuit board, the semiconductor chip, and the passive devices are subjected to package process. In order to effectively attach the solder balls to the circuit board, the soldering material is formed on the connection pads of the circuit board to provide attachments for the solder balls.
However, the trend for developing minimized semiconductor chip has resulted respective change to the conventional semiconductor package technique to achieve constantly reduced chip with more input/output terminals. Yet, the above-mentioned change would lead to a reduction in the area of the chip carrier and an increase in the number of the connection pads on the chip carrier. Therefore, the size and pitch of the connection pads are reduced to meet the demand in the current chip development. As the connection pads are minimized, the openings of the template also need to be minimized accordingly. So, the production cost is increased due to difficulty in the template development. It is also difficult for the soldering material to pass through the minimized openings of the template, creating bottleneck in terms of the process. Moreover, the precision for forming the soldering material requires not only accurate template size in the template printing technique, but it is also necessary to confirm the number of times for carrying out the template printing technique and method for cleaning the template. As the solder material is viscous, more soldering materials remain on opening walls of the template when more printing jobs are carried out. As a result, the amount and shape of the solder material used in the next printing will not match those according to the designed specification. In the actual operation, the template would have to be wiped clean after being applied to printing for certain number of times. Otherwise, it is very likely to create mismatched shape and size of the soldering material, causing process inconvenience and reduced reliability.
To resolve the above-mentioned defects, an electroplating method is adopted for forming the soldering material on the circuit board. An electroplating method performed on the organic circuit board is disclosed in a Taiwanese Publication No 508987. The method involves forming an organic insulating passivation layer on an organic circuit board having connection pads. The insulating passivation layer is formed with openings to expose the connection pads on the circuit board. A thin metal layer is formed on the circuit board. Next, an electroplating mask layer having openings therein is formed on the thin metal layer for exposing the thin metal layer covered on the connection pads, so as to form soldering material by electroplating on the exposed thin metal layer.
The conventional solder material is formed by electroplating through openings in the electroplating mask layer, with its height controlled by thickness of the electroplating mask layer. However, the solder heights and sizes for the pre-solder bumps implanted on the connection pads, surface mounting solder element, and solder element for solder ball attachment are all different. So, several separate processes are required to form solder material of different heights. If the solder material of different heights and sizes were formed, the overall fabrication time and cost would be increased. And the solder material that is formed as previously described may be loosened as a result of multiple formation and removal of the electroplating mask layer and conductive layer in the separate processes, resulting a drop in the circuit board yield. Despite of exposure and development being common steps in the semiconductor IC substrate process, a highly viscous resist resin, special spin coater, and aligner with longer wavelength are used when the resist layer used in the electroplating process has a thickness of about 25 μm, resulting an increase in fabrication cost. Therefore, fabrication time and cost would be increased as a result of separately forming the connection terminals by electroplating, while the circuit board yield is reduced accordingly.
In light of the above mentioned defects, such as limited size and increased cost of the connectional terminals formed by template printing technique, as well as reduced yield, increased fabrication time and cost, and other drawbacks associated with forming connection terminals by electroplating in the separate processes, there is an endeavor to develop a method for fabricating the connection terminals, such that connection terminals of different heights are simultaneously formed on the circuit board to reduce fabrication time, increase circuit board yield, and reduce fabrication cost.